In device fabrication, insulating, semiconducting, and conducting layers are formed on a substrate. The layers are patterned to create features and spaces. The minimum dimension or feature size (F) of the features and spaces depend on the resolution capability of the lithographic systems. The features and spaces are patterned so as to form devices, such as transistors, capacitors, and resistors. These devices are then interconnected to achieve a desired electrical function, creating an integrated circuit (IC). The formation and patterning of the various device layers are achieved using conventional fabrication techniques, such as oxidation, implantation, deposition, epitaxial growth of silicon, lithography, and etching. Such techniques are described in S. M. Sze, VLSI Technology, 2nd ed., New York, McGraw-Hill, 1988, which is herein incorporated by reference for all purposes.
In metal oxide semiconductor (MOS) devices, leakage currents need to be reduced in order to reduce power consumption. An important leakage component in MOS devices is gate-induced drain leakage (GIDL), which is caused by trap assisted band-to-band tunneling at the surface of the drain of a MOS field effect transistor (MOSFET) where the gate overlaps the drain. During fabrication, interface states in the substrate are created. These surface states increases the rate of generation of electron-hole pairs, enhancing GIDL. The effects of surface states on GIDL are described in, for example, Chen et al., IEEE Elec. Dev. Lett., 10, 216 (1989), which is herein incorporated by reference for all purposes.
One conventional technique of reducing GIDL is to increase the oxidation temperature during gate oxide formation to about 1000-1100.degree. C. Such technique is described in Joshi et al., IEEE Elec. Dev. Lett., 12, 28 (1991), which is herein incorporated by reference for all purposes. Increasing the oxidation temperature decreases surface state density in the substrate, reducing GIDL.
Increasing the oxidation temperature requires the use of a rapid thermal oxidation process (RTO). However, the use of RTO results in a gate oxide with poorer uniformity than with furnace oxidation. Non-uniformity of the gate oxide results in large variation of threshold voltages for the devices, which is undesirable.
Another technique for reducing GIDL is to implement lightly doped drain (LLD) devices. LLD devices to reduce GIDL is described in Parke et al., IEEE Trans. Elec. Dev., 39, 1694 (1992), which is herein incorporated by reference for all purposes. However, further reduction of GIDL is required for future generations of ICs, such as 256 Megabit dynamic random access memories (DRAMs).
From the above discussion, it is desirable to provide a device with lower GIDL.